Circuit For Quiz Contest : Electronic Jam
This is the design diagram of electronic jam. This jam circuit can be implemented in quiz contests in which any participator who pushes his switch (button) prior to the other participants, will get the first opportunity to answer a question. The circuit provided right here allows up to eight participants with each one assigned a unique number (1 to 8). The display will show the number of the contestant pushing his button prior to the others. Concurrently, a buzzer will also sound. Both of those, the display and also the buzzer need to be reset manually working with a general reset switch.
At first, when reset switch S9 is briefly pushed and released, all outputs of 74LS373 (IC1) transparent latch go ‘high’ because all of the input data lines are returned to Vcc by way of resistors R1 through R8. All eight outputs of IC1 are joined to inputs of priority encoder 74LS147 (IC2) as well as 8-input NAND gate 74LS30 (IC3). The output of IC3 thus becomes logic 0 which, after inversion by NAND gate N2, is implemented to latch-enable pin 11 of IC1. With all input pins of IC2 becoming logic 1, its BCD output is 0000, that is put on 7-segment decoder/driver 74LS47 (IC6) right after inversion by hex inverter gates within 74LS04 (IC5). Therefore, on reset the display will show 0.
When any one of the push-to-on switches-S1 through S8-is pushed, the affiliated output line of IC1 is latched at logic 0 level and also the display signifies the number associated with the certain switch. Simultaneously, output pin 8 of IC3 gets high, that triggers outputs of the two gates N1 and N2 to proceed to logic 0 condition. Logic 0 output of gate N2 inhibits IC1, and thus pushing of any other switch S1 through S8 doesn’t have any result. As a result, the contestant who pushes his button first, jams the display to show only his number. In the unlikely event of simultaneous pushing (within few nano-seconds difference) of more than one switch, the higher priority number (switch no.) is going to be shown. Concurrently, the logic 0 output of gate N1 drives the buzzer via PNP transistor BC158 (T1). The buzzer also the display could be reset (to display 0) by momentary pressing of reset switch S9 in order that up coming round may get started.
You may design this electronic jam circuit similar to the following preview:
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